1. Field of the Invention
The present invention relates to an inspection system, and more particularly to an inspection system used to detect defects of the pattern formed on an object to be inspected, such as a mask.
2. Background Art
In recent years, as the levels of integration and capacity of large scale integrated circuits (LSIs) increase, there has been a need to continue to reduce the width of the circuit patterns of semiconductor devices. Semiconductor devices are manufactured by a reduced projection exposure apparatus called a “stepper” using original artwork patterns with a circuit pattern formed thereon, that is, masks or reticles (hereinafter referred to collectively as masks). Specifically, the pattern on a mask is transferred to the wafer by exposure to light, thereby forming circuits on the wafer. Masks used to transfer such fine circuit patterns to the wafer are manufactured by electron beam writing apparatuses, which can write micropatterns. Further, effort has been made to develop a laser beam writing apparatus, which uses a laser beam for writing. It should be noted that electron beam apparatuses are also used to directly write a circuit pattern on a wafer.
Incidentally, since the cost to manufacture LSIs is very high, the increase of the yield is required to make the manufacture economically feasible. However, the dimensions of the patterns for LSI devices, as typified by 1-gigabit class DRAMs (random access memories), are about to be scaled down from the order of submicrons to the order of nanometers. A major cause of loss in yield is due to defects of a mask pattern. Further, since there has been a decrease in the dimensions of LSI patterns formed on semiconductor wafers, the size of pattern defects to be detected is very small. Therefore, high inspection accuracy is required of inspection systems for detecting defects of transfer masks used in LSI manufacture.
There are two known mask defect detecting methods: the die-to-die inspection method and the die-to-database inspection method. The die-to-die inspection method is used when the mask to be inspected has thereon a plurality of identical chip patterns, or a plurality of chip patterns each including an identical pattern segment. In this method, these identical chip patterns or identical pattern segments, which are to be transferred to the wafer, are compared to each other. This method permits accurate inspection using a relatively simple system configuration, since patterns on the same mask are directly compared to each other. However, this method cannot detect a defect common to both compared patterns. In the die-to-database inspection method, on the other hand, an actual pattern on a mask is compared to reference data generated from the design pattern data that was used to manufacture the mask. Thus, this method allows exact comparison of the pattern with the design pattern data, although the required system size is large since the method requires a processing system for generating a reference image. There is no choice but to use this inspection method when the mask to be inspected has only one chip pattern to be transferred to the wafer.
In die-to-die inspection system, light is emitted from a light source, and the mask to be inspected is irradiated with this light through an optical system. The mask is mounted on a table, and this table is moved so that the emitted beam of light scans the surface of the mask. Light transmitted through or reflected from the mask are acquired by image sensors, thereby forming an image thereon. The optical image thus formed on the image sensor is sent to a comparing unit as measurement data. The comparing unit compares the measurement data with reference data in accordance with an appropriate algorithm, and if they are riot identical, the mask is determined to have a defect (see, e.g., Japanese Laid-Open Patent Publication No. 2008-112178).
Conventional inspection systems are so designed as to complete a defect evaluation process (i.e., a process of determining whether the size of a detected defect is within the tolerable range) in a time approximately equal to the time required to capture an optical image of the mask by the image sensor. Specifically, each inspection system includes a defect evaluation processing unit that matches the scale of the defect evaluation process expected to be performed. However, as pattern dimensions have been scaled down, the scale of the defect evaluation process has been increased to such an extent that the time required for the process is too long as compared to the time required to capture an optical image of the mask.
Incidentally, it is not necessary to accurately control the dimensions, etc. of all the patterns formed on a mask. For example, a dummy feature or pattern, which does not serve for wiring purposes, is sometimes formed in a place where the pattern density is extremely low. No problem is presented even if this dummy feature or pattern has some “pin-hole defect” or edge roughness.
On the other hand, it is necessary to accurately control the impedance of a pattern through which a clock signal passes (i.e., a clock line), and the position and the diameter of a contact hole passing through a plurality of layers.
In order to address this problem, a method has been proposed in which the level of importance, or weight, of each pattern is added to design pattern data as pattern importance information, and pattern data and pattern importance information are input to the inspection system. For example, Japanese Laid-Open Patent Publication No. 2009-105430 discloses a method for simulating a lithographic design comprised of a number of polygons arranged in a predetermined configuration. Specifically, referring to FIG. 4 of this publication, an aerial image is generated using a bitmap image available from the polygon design database (box 126), and resist modeling or simulation is performed using this aerial image (box 128).
Further, Published Japanese Translation of PCT Application No. 2001-516898 states as follows: “In any mask inspection system, the important decision to make is whether a given defect will ‘print’ on the underlying photoresist in a lithography process under specified conditions. If a mask defect does not print or have other effect on the lithography process, then the mask with the defect can still be used to provide acceptable lithography results. Therefore, one can avoid the expense in time and money of repairing and/or replacing masks whose defects do not print.” This publication discloses a method of receiving a defect area image including an image of a portion of a mask and generating a simulated image. This simulated image includes a simulation of an image which would be printed on the wafer.
However, if such a method is performed within the inspection system, an increase in the scale of the defect evaluation process results. Further, although in the method of the above PCT publication the lithography simulation is performed by a simulator in the inspection system, it will be understood that the simulation may be carried out by a general purpose simulator, which is convenient in use. It should be noted that some simulators cannot perform resist modeling or simulation although they can generate an aerial image of a wafer. That is, these simulators can perform basic simulation, but not higher level simulation. It is disadvantageous that the type of simulator used restricts the information that can be obtained.
It is, therefore, an object of the present invention to provide an inspection system capable of facilitating defect evaluation and capable of performing a defect evaluation process in conjunction with a highly versatile simulator.
Other challenges and advantages of the present invention are apparent from the following description.